Time-to-digital converters (TDCs) have been developed for various transducer applications, such as laser range finding, and for open-loop time-domain applications, such as Global Positioning System (GPS) decoders. Known TDCs generally cannot operate at comparatively high clock rates or meet the noise performance required for low phase-noise synthesis applications. These known TDCs generally rely on gate delay as the basic unit of time measurement, which limits the time resolution and thus the quantization noise floor. In addition, meta-stability issues associated with asynchronous timing presents design challenges. Therefore, implementation of high performance all-digital phase-lock loops (ADPLLs), for example, relying on TDCs has been hampered because known TDCs have substantially worse noise performance than phase detectors used in analog PLLs.